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Espressif Systems /ESP32-S3 /UHCI0 /INT_CLR

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Interpret as INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_START_INT_CLR)RX_START_INT_CLR 0 (TX_START_INT_CLR)TX_START_INT_CLR 0 (RX_HUNG_INT_CLR)RX_HUNG_INT_CLR 0 (TX_HUNG_INT_CLR)TX_HUNG_INT_CLR 0 (SEND_S_REG_Q_INT_CLR)SEND_S_REG_Q_INT_CLR 0 (SEND_A_REG_Q_INT_CLR)SEND_A_REG_Q_INT_CLR 0 (OUTLINK_EOF_ERR_INT_CLR)OUTLINK_EOF_ERR_INT_CLR 0 (APP_CTRL0_INT_CLR)APP_CTRL0_INT_CLR 0 (APP_CTRL1_INT_CLR)APP_CTRL1_INT_CLR

Description

Interrupt clear bits

Fields

RX_START_INT_CLR

Set this bit to clear UHCI_RX_START_INT interrupt.
TX_START_INT_CLR

Set this bit to clear UHCI_TX_START_INT interrupt.
RX_HUNG_INT_CLR

Set this bit to clear UHCI_RX_HUNG_INT interrupt.
TX_HUNG_INT_CLR

Set this bit to clear UHCI_TX_HUNG_INT interrupt.
SEND_S_REG_Q_INT_CLR

Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt.
SEND_A_REG_Q_INT_CLR

Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt.
OUTLINK_EOF_ERR_INT_CLR

Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt.
APP_CTRL0_INT_CLR

Set this bit to clear UHCI_APP_CTRL0_INT interrupt.
APP_CTRL1_INT_CLR

Set this bit to clear UHCI_APP_CTRL1_INT interrupt.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data